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XOCLCC6EVB
EVALUATION BOARD MAP
4
3
H
L
OE
2
VDD
1
J1
5
H
L
11
10
6
7
FSEL
DUTGND
8
SMAGND
9
C3
C4
J2
Figure 2. Evaluation Board Layout
Table 1. EVALUATION BOARD MAP DESCRIPTION
Number
1
2
3
4
5
6
7
8
9
10
11
Description
DUT PIN6 Positive supply connection anvil and test point.
Decoupling capacitors. See BOM/board schematic for details.
DUT PIN 4 OE jumper header to force logic HIGH (Active) or LOW (Outputs Disabled to High Impedance).
Leave open or use jumper to force HIGH (OE Pin defaults HIGH when left floating) (see Figure 3 below)
OE connection anvil and test point.
DUT PIN 2 FSEL jumper header to force logic HIGH or LOW. FSEL Pin defaults HIGH when left floating. (see
Figure 3 below)
FSEL connection anvil and test point.
Device ground (DUTGND) connection anvil and test point.
DUT PIN 3 GND/SMAGND jumper header to force DUTGND connection to SMAGND. (see Figure 3 below)
SMAGND connection anvil and test point.
SMA outputs (CLK/CLK).
6 pin CLCC 5mmX7mm DUT (Device under test).
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2
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